

module Subtracter
    #(
        parameter IWID=12,
        parameter OWID=32
    )
    (
        input wire signed [IWID-1:0] i_sub1,
        input wire signed [IWID-1:0] i_sub2,
        input wire i_clk,
        input wire i_rst,
        output reg signed [OWID-1:0] o_diff
    );

    wire signed [OWID-1:0] sub_result;

    assign sub_result=i_sub1-i_sub2;

    always@(posedge i_clk or posedge i_rst) begin
        if(i_rst) begin
            o_diff<='b0;
        end
        else begin
            o_diff<=sub_result;
        end
    end

endmodule